The present invention relates generally to a charge pump current compensating circuit that may be used for a phase-locked loop (PLL) and/or a delay-locked loop (DLL) and more particularly to charge pump current compensating circuit that provides compensation so that charging current and discharge current may be essentially equal.
A charge pump current compensating circuit can be used to compensate current supplied to a low-pass filter (LPF) of a phase locked loop (PLL) and/or a delay locked loop (DLL).
Referring to FIG. 6, a block schematic diagram of a phase locked loop (PLL) is set forth and given the general reference character 600.
PLL 600 includes a phase comparator 1, a conventional charge pump circuit (CP) 2, and a voltage controlled oscillator (VCO) 3.
Phase comparator 1 receives a reference input signal REFERENCE INPUT and an oscillating output signal OUTPUT and provides an up pulse UP and down pulse DN. Phase comparator 1 compares each phase of reference input signal REFERENCE INPUT and oscillating output signal OUTPUT. When reference input signal REFERENCE INPUT leads oscillating output signal OUTPUT, up pulse UP is provided. When reference input signal REFERENCE INPUT lags oscillating output signal OUTPUT, down pulse DN is provided. Conventional charge pump circuit 2 generates control current for charging or discharging a capacitor using the up pulse UP or the down pulse DN provided from phase comparator 1. Voltage controlled oscillator 3 provides oscillating output signal OUTPUT based upon a control voltage generated by conventional charge pump circuit 2. In this way, conventional charge pump circuit 2 in phase locked loop 600 controls charging current and discharge current for a capacitor of a low pass filter (LPF). By using a low pass filter (providing a sufficiently large capacitor value), the stability of an oscillating output signal OUTPUT is increased.
Referring now to FIG. 7, a circuit schematic diagram of conventional charge pump circuit 2 is set forth.
Conventional charge pump circuit (CP circuit) 2 includes PMOS (p-type metal oxide semiconductor) transistors (P1 to P4), NMOS (n-type metal oxide semiconductor) transistors (N1 to N6), constant current source 11, and capacitor C.
Constant current source 11 has a current amplified by a current mirror that includes PMOS transistors (P2 and P4) for charging capacitor C and by a current mirror formed by NMOS transistors (N2 and N4) for discharging capacitor C. In this way, a desired constant current (for example, ten times current 11) is used to provide a predetermined voltage Vcont on capacitor C forming a low pass filter. Up pulse UP is provided to the gate of PMOS transistors P1 to control the charging current and down pulse DN is provided to the gate of NMOS transistor N1 to control the discharge current. Conventional charge pump circuit 2 varies the potential of voltage Vcont on capacitor C forming a low pass filter and thereby varying a frequency or delay time in phase locked loop 600.
Referring to FIG. 8, a graph illustrating transfer characteristics of conventional charge pump circuit 2 is set forth.
As shown in FIG. 8, symmetrical voltage-current characteristics of PMOS transistor P2 and NMOS transistor N2 are illustrated with solid lines. A stable operating point of conventional charge pump circuit 2 gives a potential of voltage Vcont at point Al that can be supplied to voltage controlled oscillator VCO. However, when the output impedances of PMOS transistor P2 and NMOS transistor N2 varies due to process variations, the values (Ids) of charging current and discharge current become different.
For example, when the output impedance of NMOS N2 varies (from a characteristic illustrated as the solid line in FIG. 8 to a characteristic shown as a dashed line) due to process variations, voltage Vcont has a stable operating point at point A2. As a result, voltage Vcont can varies to point A2 through charge and discharge.
Referring to FIG. 9, a graph illustrating transfer characteristics of conventional charge pump circuit 2 is set forth. The transfer characteristics of FIG. 9 illustrate maximum and minimum points at which voltage Vcont and charging/discharge current are locked. FIG. 9 illustrates the maximum and minimum values at which NMOS and PMOS transistors (N2 and P2) are locked. When PMOS P2 is locked at point (A1), NMOS transistor N2 is locked at point (B2) or when PMOS P2 is locked at point (A2), NMOS transistor N2 is locked at point (B1) respectively. In this way, values of charging and discharging current (Ids) become different. As a result, a desired voltage Vcont cannot be acquired because of variations of points (B2) through discharge and variation of points (A1) through charging, or a desired voltage Vcont cannot be acquired because of variations of points (B1) through discharge and variation of points (A2) through charging. Also, the output impedances decrease as the gate length (L) of transistors forming charge pump is reduced. Thus, as transistors are reduced in size, process variations may cause greater effects and the difference between charging current and discharge current can become even greater.
A conventional charge pump circuit used for a PLL is described above. However, a conventional charge pump circuit can be similarly used for a DLL.
In a conventional charge pump circuit as described above, a charging current and a discharge current for a capacitor may be different due, for example, to process variations. Therefore, a conventional charge pump circuit may not keep an output potential (Vcont) in a desired range as illustrated in FIGS. 8 and 9. Due to this, the output potential (Vcont) may deviate from a desired range which may cause the performance of a PLL or DLL including the conventional charge pump circuit to deteriorate.
In view of the above discussion, it would be desirable to provide a charge pump current compensating circuit which may provide an output potential essentially constant or in a desired range.
According to the present embodiments, a charge pump current compensating circuit (4) including feedback so that a difference between a charging current and a discharging current may be reduced is disclosed. A charge pump current compensating circuit may include a current source leg, a first current mirror leg, a second current mirror leg, and a compensation circuit. A compensation circuit may provide compensation to control insulated gate field effect transistors (IGFETs) so that a charging current and a discharging current may be essentially the same even when output impedances of IGFETs are different.
According to one aspect of the embodiments, a charge pump compensating circuit may control a charge current for charging a capacitor and a discharge current for discharging a capacitor based on a phase comparator output. The charge pump current compensating circuit may include a compensation circuit coupled to receive a voltage output from the capacitor and provide compensation so that the charge current may be essentially the same value as the discharge current.
According to another aspect of the embodiments, the capacitor may be a capacitance of a low pass filter.
According to another aspect of the embodiments, the compensation circuit may prevent the voltage output from essentially varying.
According to another aspect of the embodiments, the compensation circuit may compensate for differences in a first output impedance of a p-type insulated gate field effect transistor (IGFET) and a second output impedance of a n-type IGFET so that the charge current may be essentially the same value as the discharge current.
According to another aspect of the embodiments, the charge pump current compensating circuit may include an essentially constant current circuit and a current mirror circuit. The essentially constant current circuit may provide a bias output. The current mirror circuit may receive the bias output and provide the charging current through a p-type IGFET having a control gate coupled to receive a compensation signal from the compensation circuit.
According to another aspect of the embodiments, the charge pump current compensating circuit may include an essentially constant current circuit and a current mirror circuit. The essentially constant current circuit may provide a bias output. The current mirror circuit may include a first current mirror leg and a second current mirror leg receiving the bias output. The first current mirror leg may provide the charging current and the discharge current at a first current mirror leg node. The compensation circuit may provide compensation by detecting a potential difference between the first current mirror leg node and a second current mirror leg node of the second current mirror leg.
According to another aspect of the embodiments, the charge pump current compensating circuit may be used in a phase locked loop or a delay locked loop.
According to another aspect of the embodiments, a charge pump current compensating circuit may include a current source leg, a first current mirror leg, a second current mirror leg, and a first compensation circuit. The current source leg may provide a bias potential. The first current mirror leg may receive the bias potential and provide a first current mirror leg voltage output. The second current mirror leg may receive the bias potential and provide charging current and discharge current for charging and discharging a capacitance at a second current mirror leg voltage output. The first compensation circuit may receive the first current mirror leg voltage output and the second current mirror leg voltage output and provide a first compensation potential to a control gate of a second current mirror leg insulated gate field effect transistor (IGFET) included in the second current mirror leg.
According to another aspect of the embodiments, the first compensation circuit may provide the first compensation potential to a first current mirror leg IGFET included in the first current mirror leg.
According to another aspect of the embodiments, the charge pump compensating circuit may include a third current mirror leg and a second compensation circuit. The third current mirror leg may receive the bias potential and provide a third current mirror leg voltage output. The second compensation circuit may receive the first current mirror leg voltage output and the third current mirror leg voltage output and provide a second compensation potential to a control gate of a third current mirror leg IGFET included in the third current mirror leg.
According to another aspect of the embodiments, the first compensation circuit may include a first sense amplifier and the second compensation circuit may include a second sense amplifier.
According to another aspect of the embodiments, the second current mirror leg IGFET is a p-type IGFET.
According to another aspect of the embodiments, the first current compensation circuit may provide compensation so that the charge current is essentially the same value as the discharge current.
According to another aspect of the embodiments, the charge pump current compensation circuit is used in a phase locked loop or a delay locked loop.
According to another aspect of the embodiments, a charge pump current compensating circuit may include a current source, a first amplifier, a first insulated gate field effect transistor (IGFET), a second IGFET, a third IGFET, a fourth IGFET, a fifth IGFET, a sixth IGFET, a seventh IGFET, and an eighth IGFET. The current source may be disposed between a first power source and a first bias node. The first amplifier may include a first amplifier input, a second amplifier input, and a first amplifier output. The first IGFET may be of a first conductivity type and may have a first IGFET source connected to the first power source, a first IGFET gate connected to a second power source, and a first IGFET drain coupled to the second IGFET source. The second IGFET may have the first conductivity type and may have a second IGFET drain connected to the first amplifier input and a fifth IGFET drain. The third IGFET may have the first conductivity type and may have a third IGFET source connected to the first power source, a third IGFET gate connected to receive a first input signal, and a third IGFET drain connected to a fourth IGFET source. The fourth IGFET may have the first conductivity type and may have a fourth IGFET gate connected to receive the first amplifier output and a fourth IGFET drain connected to the second amplifier input and a seventh IGFET drain. The fifth IGFET may have-a second conductivity type and may have a fifth IGFET source connected to a sixth IGFET drain and a fifth IGFET gate connected to the first bias node. The sixth IGFET may have the second conductivity type and may have a sixth IGFET source connected to the second power source and a sixth IGFET gate connected to the first power source. The seventh IGFET may have the second conductivity type and may have a seventh IGFET source connected to an eighth IGFET drain and a seventh IGFET gate connected to the first bias node. The eighth IGFET may have the second conductivity type and may have an eighth IGFET gate connected to receive a second input signal and an eighth IGFET source connected to the second power source.
According to another aspect of the embodiments, the first conductivity type is p-type and the second conductivity type is n-type.
According to another aspect of the embodiments, the gate of the second IGFET is connected to receive the first amplifier output.
According to another aspect of the embodiments, the charge pump current compensating circuit may include a second amplifier, a ninth IGFET, a tenth IGFET, an eleventh IGFET, and a twelfth IGFET. The second amplifier may include a third amplifier input, a fourth amplifier input connected to the first amplifier input, and a second amplifier output. The ninth IGFET may have the first conductivity type and may have a ninth IGFET source connected to the first power source, a ninth IGFET gate connected to the second power source, and a ninth IGFET drain connected to a tenth IGFET source. The tenth IGFET may have the first conductivity type and may have a tenth IGFET gate connected to the second amplifier output and a tenth IGFET drain connected to the third amplifier input and an eleventh IGFET drain. The eleventh IGFET may have the second conductivity type and may have an eleventh IGFET source connected to a twelfth IGFET drain and an eleventh IGFET gate connected to the first bias node. The twelfth IGFET may have the second conductivity type and may have a twelfth IGFET source connected to the second power source and twelfth IGFET gate connected to the first power source.
According to another aspect of the embodiments, the first conductivity type may be p-type and the second conductivity type may be n-type.
According to another aspect of the embodiments, the fourth IGFET may provide a first current and the second IGFET may provide a second current and the first and second currents are essentially equal.